The present invention relates to a method of layout of a semiconductor integrated circuit, and more particularly to a routing method thereof.
Generally, a gate array or cell-based system integrated circuit device has been designed as follows. Function cells which form basic logic cells have previously been prepared by automatic placement of the function cells and subsequent automatic routing of the interconnections between the function cells so as to design any desired logic circuits.
FIG. 1 is a flow chart illustrative of conventional automatic placement and subsequent automatic routing. Function cell placement 101 is carried out along with a floor plan having previously been prepared in consideration of density of interconnections between the function cells. Subsequently, routing 102 of interconnections between the function cells is carried out along with routing channels having previously been defined. Finally, verifying processes 103 and 104 are carried out to verify the correspondence of the currently designed logic circuit to the desired logic circuit. If the correspondence can be verified. then the layout processes are terminated. If, however, no correspondence can be verified, then the function cell placement 101 or the routing 102 is again carried out until the correspondence can be verified.
The above routing process 102 is carried out for power interconnections which are provided for supplying power and signal interconnections which are provided for transmitting signals between input and output terminals of the function cells. Particularly, the capacity of the signal interconnections are mainly dominated by a capacitance between substrates and a capacitance between different level interconnection layers, whilst a capacitance between adjacent two interconnections in the same level is so small as almost ignoble. For those reasons, it is general that the routing is carried out so that the length of the interconnection is as short as possible to minimize the interconnection delay in transmission of signals.
Recently, however, the micro-lithography techniques have progressed so that the width of the interconnections and the distance between the same may be defined in the one micron order, and thus the parasitic capacitance between the adjacent pairs of interconnections in the same level can no longer be ignored. Assuming that a 2-micron silicon oxide film as an interlayer insulator is formed on a silicon substrate and that interconnections having a thickness of 1 micron and a width of 1 micron are formed over the silicon substrate so as to have a distance of 1 micron between the adjacent two interconnections, a total capacitance of a single signal interconnection is 0.24 pF/mm whilst a parasitic capacitance of the adjacent two interconnections is 0.14 pF/mm which is 60% of the total capacitance.
In order to settle the above issue of the large parasitic capacitance of the adjacent two interconnections on which clock signals are transmitted, the following layout was proposed which is disclosed in the Japanese laid-open patent publication No. 4-207071. FIG. 2 is a plan view illustrative of an automatic routing of interconnections between function cells in the semiconductor integrated circuits. First level signal interconnections 1A, 1B, 1C, 1D, and 1E as well as second level signal interconnections 2A, 2B, 2C, 2D, 2E, 2F, 2G and 2H are illustrated as channels for layout of the first level and second level interconnections, part of which are for clock signal transmission. There are provided first level signal interconnections 12, 13 and 14 on which normal logic signals are transmitted as well as second level signal interconnections 23, 24, 25, 26 and 27 on which the normal logic signals are transmitted. Further, through holes 33 and 34 are formed to provide connections between the first level and second level interconnections. A first level clock signal interconnection 11 on which a clock signal is transmitted is furthermore provided as well as a second level clock signal interconnections 21 and 22 on which clock signals are transmitted are moreover provided. The first level and second level clock signal interconnections 11 and 21 are connected to each other through a though hole 31. The first level and second level clock signal interconnections 11 and 22 are connected to each other through a though hole 32. The clock signal is transmitted from the second level clock signal interconnection 21 to the second level clock signal interconnection 22.
As illustrated in FIG. 2, a distance I.sub.1 between the first level clock signal interconnection 11 and the first level signal interconnection 13 is equal to a distance I.sub.2 between the first level clock signal interconnection 11 and the first level signal interconnection 14. The distance I.sub.1 and I.sub.2 are two times of a normal distance I.sub.3 between the first level clock signal interconnection 12 and the first level signal interconnection 13. A distance L.sub.1 between the second level clock signal interconnection 21 and the second level signal interconnection 23 is equal to a distance L.sub.2 between the second level clock signal interconnection 21 and the second level signal interconnection 24. A distance L.sub.3 between the second level clock signal interconnection 22 and the second level signal interconnection 26 is equal to the distance L.sub.1 and L.sub.2. A distance L.sub.4 between the second level clock signal interconnection 22 and the second level signal interconnection 27 is equal to the distance L.sub.1, L.sub.2 and L.sub.3. The distances L.sub.1, L.sub.2 and L.sub.3 and L.sub.4 are each two times a distance L.sub.5 between the second level interconnection 25 and the second level signal interconnection 26.
In the prior art, the routing processes of the clock signal interconnections 11, 21 and 22 are carried out separately from the routing processes of the logic signal interconnections 12, 13, 14, 23, 24, 25, 26 and 27 so that the width of the signal interconnections and the distance between the same are defined by the minimum width of the interconnections and the minimum distance between them which are restricted by the micro-lithography technique, whilst the distance between the clock signal interconnections is set at a predetermined distance.
The above conventional layout method, however has the following disadvantages or problems. Whereas it is possible to reduce the parasitic capacitance between the clock signal interconnections, it is difficult to reduce the parasitic capacitance between the normal signal interconnections. For those reasons, as micro-lithography techniques advance resulting in a reduction in distance between the adjacent pairs of signal interconnections, the parasitic capacitance between those signal interconnections increases. The increase in the parasitic capacitance between the adjacent pair of signal interconnections results in an increase in time-delay of signal transmissions on those signal interconnections. This degrades the frequency performance of the integrated circuit device.
Further, the time-delay of signal transmissions on the signal interconnections is not precisely predictable until after the actual routing has been carried out, for which reason as a ratio of the time-delay of the signal transmission to the signal transmission time is increased, it becomes difficult to predict performances of the device in the logic deign level prior to the layout. In order to settle this problem, it is required to carry out a layout design with excessively large margins.
On the other hand, the parasitic capacitance between the first level and second level signal interconnections may be reduced by increasing the thickness of the inter-layer insulator between the first level and second level interconnection layers. Notwithstanding, such technique is inapplicable to reduce the adjacent two signal interconnections in the same level, for which reason it is difficult to reduce the parasitic capacitance between the adjacent two signal interconnections.